1. Field of the Invention
This invention relates to the field of electronic systems, and in particular to systems comprising components having multiple clocked components or modules.
2. Description of Related Art
Large scale systems often contain multiple components that communicate via a common bus. In a conventional common bus system, a bus-clock is provided to synchronize the communications among the modules. That is, reliable bus communications among modules requires that the data being communicated is stable at the times when the communication is to actually occur. The bus-clock identifies these stable communication times. Conventionally, a module writes its data to the bus sufficiently ahead of the communication time so that it is stable when the communication time occurs, and a module reads the data from the bus when the communication time occurs, as identified by a bus-clock transition.
Due to propagation delays, component delays, and the like, the actual time that a module reads the data will not coincide exactly with the time that the bus-clock transition occurs, and therefore the writing module must maintain the stability of the data within some specified tolerance band before and after the transition, and no other module may initiate a write to the bus, for example, in anticipation of the next bus-clock transition, within this specified tolerance band. Each module that reads data from the bus must effect its read operation within this tolerance band.
In general, the width of the tolerance band before and after the bus-clock transitions limits the speed at which the bus-clock transitions can occur, and therefore limits the achievable data transfer rate via the bus. Narrowing the tolerance band, however, requires tighter design and fabrication rules to assure that modules conform to the tighter limits, and therefore increase the cost of the modules. In a typical design, the ever increasing demand for higher system performance forces the bus-clock speed to xe2x80x9cpush the limitxe2x80x9d, allowing for as little tolerance as possible to achieve the highest speed possible. Because the actual propagation delays, component delays, and the like are not determinable until after the effects of the actual placement and routing of each module on a chip or board are determined, the modules are typically iteratively designed and redesigned to assure that the data is read from or written to the bus at precisely the right time. That is, each module""s clock is adjusted or redesigned so that it is synchronous in phase with the bus-clock at its particular location on the chip or board, with its particular routing path and associated delay parameters. This iterative design process is costly, and often results in significant program schedule slippage as the interactions of each of the modules and each of the design or layout changes produce an increasingly difficult set of design and timing tradeoffs and constraints.
To reduce the likelihood of an iterative design process, alternative techniques have been developed to increase the likelihood of conforming to tight clock tolerance requirements. A common technique is the use of self-synchronizing design techniques. For example, to assure that the input or output of a module remains synchronous to the bus-clock regardless of the placement of the module on the chip or board, the module can include a Phase-Locked-Loop (PLL), which, as its name implies, locks the phase of the module""s data transfer clock to the phase of the bus-clock. That is, rather than physically adjusting each module""s clock to match the phase of the bus-clock, the PLL effects this matching electronically and automatically. Because the layout parameters of each module affect each module""s phase relationship with the bus-clock, each module in this alternative must include a PLL to effect an accurate phase matching.
Although the use of self-synchronizing modules substantially reduces the number of design iterations required, there are additional costs associated with adding a PLL circuit to each module. These costs include the additional cost of the components used, the additional cost of testing each PLL, the consumption of area on the chip or board to accommodate each PLL, and the like. Addition, conventional PLLs include analog components, which, as is known in the art, are inherently more difficult and costly to design and fabricate than digital components, and which do not scale as easily to newer technologies as digital components. Also, each PLL consumes a significant amount of power compared to digital components.
It is an object of this invention to provide a clock architecture that provides for a reliable and robust bus-system interface. It is another object of this invention to provide a clock architecture that is modular. It is another object of this invention to provide a clock architecture that is scalable. It is another object of this invention to provide a clock architecture that is easy to test. It is another object of this invention to provide a clock architecture that reduces the complexity associated with system tests. It is another object of this invention to provide a clock architecture that consumes substantially less power than a PLL based design.
These objects, and others, are achieved by providing a clock module that operates in conjunction with the generation of the bus-clock signal to provide a combination of module-clocks that can be relied upon to provide an adequate safety margin for data transfers among processing modules at the speed of the bus-clock. In a preferred embodiment, a master-clock generates the bus-clock and a sample-clock, the sample-clock having a predetermined phase relationship with respect to the bus-clock. Base-clocks at each of the frequencies required for each processing module are generated in the conventional manner, and, in accordance with this invention, are sampled by the sample-clock to produce sampled module-clocks that are provided to each corresponding processing module. By sampling each base-clock with a sample-clock that has a corresponding predetermined phase relationship with respect to the bus-clock, each module-clock will have a predetermined phase relationship with respect to the bus-clock. By selecting the predetermined phase relationship appropriately, an optimal data transfer speed can be achieved.